Chap 6 Registers & Register Transfers¶

寄存器¶

Registers are useful for storing and manipulating information; counters are employed in circuits that sequence and control operations in a digital system.

clock skew

寄存器单元¶

A single-bit cell of an iterative combinational circuit, connected to a flip-flop that provides the output, forms a two-state sequential circuit called a register cell

• 寄存器的功能函数；
• 一般指寄存器传输；
• 控制信号构成；
• 寄存器的输入数据；
• 有哪些输入数据、是否需要预先处理等；

寄存器传输¶

Datapaths are defined by their registers and the operations performed on binary data stored in the registers.

1. 系统中的寄存器集合；
2. 对于数据的操作；
3. 监督操作序列的控制；

Note that:

the term “microoperation,” as used here, does not refer to any particular way of producing the control signals: specifically, it does not imply that the control signals are generated by a control unit based on a technique called microprogramming.

寄存器传输操作 & 寄存器传输语言¶

Little-endian & Big-endian

$if\, (K_1 = 1) \,then\, (R2 \leftarrow R1)$

$K_1 : R2 \leftarrow R1$

寄存器传输的实现¶

基于总线实现传输¶

共有 MUX 实现¶

• 优势：
• 电路更精简，成本更低，随着寄存器增加这个特点更加明显；
• 劣势：
• 同一时刻内总线只能传输一个数据，即只有一个数据源(source)；
• 同一时钟周期内只有一个数据能传输到别的地方，例如交换操作就需要至少两个 bus 才能实现；

三态门实现¶

Three-state buffer outputs can be connected together to form a multiplexed output line.

MUX 实现相对比，三态门实现方式如下：

If the three-state buffers are enabled, then the lines are outputs; if the three-state buffers are disabled, then the lines can be inputs.

微操作及其实现¶

A microoperation is an elementary operation performed on data stored in registers or in memory.

1. 转移，transfer microoperations，将数据从一个寄存器转移到另外一个寄存器；
2. 算术，arithmetic microoperations，对数据的算术运算操作；
3. 逻辑，logic microoperations，对数据的逻辑运算操作；
4. 位移，shift microoperations，对数据的位移操作；

A given microoperation may be of more than one type. For example, a 1s complement operation is both an arithmetic microoperation and a logic microoperation.

算术¶

Multiplication and division are not listed in Table 6-3. Multiplication can be represented by the symbol * and division by /. These two operations are not included in the basic set of arithmetic microoperations because they are assumed to be implemented by sequences of basic microoperations. However, multiplication can be considered as a microoperation if implemented by a combinational circuit. In such a case, the result is transferred into a destination register at the clock edge after all signals have propagated through the entire combinational circuit

$\begin{array}{l} &\overline{X}K_1:R_1\leftarrow R_1 + R_2 \\ &XK_1:R_1\leftarrow R_1 + \overline{R_2} + 1 \end{array}$

$\begin{array}{l} a \cdot b & = & a \cdot (b_{n-1}b_{n-2}...b_1b_0)_2 \\ & = & a \cdot \left[ (b_{n-1}0...00)_2 + \cdot (0b_{n-2}...00)_2 + ... + \cdot (00...b_10)_2 + \cdot(00...0b_0)_2 \right]\\ & = & a \cdot \sum_{i = 0} ^{n-1} b_i \cdot 2^{i} \\ & = & a \cdot \sum_{i = 0} ^{n-1} b_i \;\mathrm{<<}\; i \;\;\; \text{where "<<" means "Shift Left"} \end{array}$

位移¶

串行实现¶

1 100 1 ? ? ? 1???
2 10 0 1 ? ? 01??
3 1 0 0 1 ? 001?
4 1 0 0 1 1001
5 ? 1 0 0 ?100
6 ? ? 1 0 ??10
7 ? ? ? 1 ???1

并行化¶

• 纵向观察右侧的四个 FF，可以发现基本上就是串行位移实现，只不过其输入不再是直接从上一个 FF 那边拿来的；
• 四个 FF 的输入是类似的，所以我们仅关注最上面的那三个与门和一个或门，表示数据输入有三个可能的来源；
1. 第一个与门，$$F_i=Shift \cdot SI$$（对于后面几个 FF，则是 $$F_i=Shift \cdot FF_{i-1}$$），可以发现，此时电路的行为与 串行位移实现 一致；
• $$Shift$$1 时，SHR 表现为「每个周期执行一次位移」；
2. 第二个与门，$$F_i=\overline{Shift} \cdot Load \cdot D_i$$，此时电路的行为是使用比特向量对每一个 FF 赋值，即 并行载入
• $$\overline{Shift} \cdot Load$$1 时，SHR 表现为「并行载入」；
3. 第三个与门，$$F_i=\overline{Shift} \cdot \overline{Load} \cdot Q_i$$，此时电路的行为是保持上一周期的结果；
• $$\overline{Shift} \cdot \overline{Load}$$1 时，SHR 表现为「保持」；

$\begin{array}{rl} Shift :& Q\leftarrow \mathrm{sl}\; Q \\ \overline{Shift}\cdot Load :& Q\leftarrow D \\ \overline{Shift}\cdot \overline{Load} :& Q\leftarrow Q \end{array}$

双向位移寄存器¶

$\begin{array}{rl} \overline{S_0} \cdot \overline{S_1} :& Q \leftarrow Q\\ S_0 \cdot \overline{S_1} :& Q\leftarrow\mathrm{Sl}\; Q \\ \overline{S_0} \cdot S_1 :& Q\leftarrow\mathrm{Sr}\; Q \\ S_0 \cdot S_1:& Q\leftarrow D \end{array}$

计数器¶

行波计数器¶

• 上图中，下一个 FF 的时钟来自于上一个 FF 的输出取反，也就是对于上升沿触发的 FF 来说，下一个 FF 会在上一个 FF 的输出从 10 时自反，所以是 正向计时(Upward Counting)
• 反之，如果下一个 FF 的时钟来自于上一个 FF 的直接输出，也就是对于上升沿触发的 FF 来说，下一个 FF 会在上一个 FF 的输出从 01 时自反，所以是 逆向输出(Downward Counting)

同步计数器¶

(b) 的蓝色部分替换 (a) 的蓝框部分为第二种。两种分别为 门串行实现 和 门并行实现。

$\begin{array}{rl} D_{A0} = & Q_0 \oplus EN \\ D_{A1} = & Q_1 \oplus \left( (Q_0 \cdot \overline{S} + \overline{Q_0} \cdot S) \cdot EN \right) \\ D_{A2} = & Q_2 \oplus \left( (Q_0 \cdot Q_1 \cdot \overline{S} + \overline{Q_0} \cdot \overline{Q_1} \cdot S) \cdot EN \right) \\ D_{A3} = & Q_3 \oplus \left( (Q_0 \cdot Q_1 \cdot Q_2 \cdot \overline{S} + \overline{Q_0} \cdot \overline{Q_1} \cdot \overline{Q_2} \cdot S) \cdot EN \right) \end{array}$

Mod N 计数器

寄存器传输的控制¶

Control Unit

• Programmable sys
• instructions (usually stored in memory RAM/ROM)
• program counter
• Nonprogrammable sys

• focus on this
• State machine diagrams for Control Unit design.
• Write a detailed system specification.

• Define all external data and control input signals, all external data, control, and status output signals, and the registers of the datapath and control unit.
• Find a state machine diagram for the system including the register transfers in the datapath and in the control unit.
• Define internal control and status signals. Use these signals to separate output conditions and actions, including register transfers, from the state diagram flow and represent them in tabular form.
• Draw a block diagram of the datapath including all control and status inputs and outputs. Draw a block diagram of the control unit if it includes register transfer hardware.
• Design any specialized register transfer logic in both the control and datapath.
• Design the control unit logic.
• Verify the correct operation of the combined datapath and control logic. If verification fails, debug the system and reverify it.